Marc Majoral (Sabadell, 1974) received his M.S. degree in Electrical Engineering from the Polytechnic University of Catalonia (UPC) in 1998. He also holds a Master degree in Research on Information and Communications Technologies (MERIT) from the UPC since 2014.
Marc joined CTTC in January 2007. In the period 1999 – 2006 he worked in the Cochlear Technology Centre in Belgium, where he implemented signal processing strategies for cochlear implants. In 1999 he worked in the Signal Theory and Communications department in the Polytechnic University of Catalonia (UPC), where he was involved in Digital Signal Processing (DSP) programming for mobile communications. In 1998 he worked as a software developer in Bull-SP, Barcelona, Spain. During 1997 he was granted an undergraduate scholarship in the IT department in Hewlett-Packard, Sant Cugat del Vallès, Spain.
Marc works on the design and development of real-time signal processing communication devices, computationally intensive DSP algorithms, Software-Defined Radio (SDR) systems, Field Programmable Gate Array (FPGA) – based systems and embedded systems. He has been involved in various industrial projects (GNSS_IN_SPACE, RADPARK, Coupled-ETC, LTE LISTEN MODE – TDD-LTE Physical Layer, ULTRAMUMO, MUMO and R@ILNET) and public funded projects (ARISTIDES, AUDITOR). In the Coupled-ETC project he also worked as WP leader for the implementation tasks. In 2017 and 2018 he participated as a CTTC internship supervisor for the The Overseas Internship Scheme (OIS) summer training programme by the CityU in Hong Kong. He is also involved in some research dissemination activities: presentation of the GNSS_IN_SPACE Project at ESA, in SEFUW: SpacE FPGA Users Workshop, 4th Edition (2018), presentation of a candidate project in the IESE Barcelona Technology Transfer Group (IESE-BTTG 2017).
Summary of the project contributions:
GNSS_IN_SPACEII: design, implementation, testing and verification.
GNSS_IN_SPACE (ESA, industry): design, implementation, testing and verification of an FPGA architecture for an All-Programmable System-On-Chip based Space GNSS Receiver prototype.
RADPARK (industry): contribution to the analysis of various HW alternatives for the project.
Coupled-ETC (ESA, industry): WP leader of the implementation tasks and developer. Design, development, system integration, testing and verification of an FPGA-based TT&C Coupled Enhanced Turbo Codes Demodulator and Decoder.
LTE LISTEN_MODE (industry): Design, implementation and testing.
ULTRA high capacity multicarrier modulation modem for power line communications (ULTRAMUMO, industry): design, implementation, testing and verification. Coordination of the implementation activities.
MUMO (industry): design, implementation, testing and verification.
AUDITOR (European): design, implementation, testing and verification of an FPGA-based GNSS Receiver prototype for precision agriculture.
R@ILNET: extention of the FPGA design in order to increase the flexibility of the DVBT phy layer.
Summary of his involvment in project proposals:
ARISTIDES (2019): technical contribution.
GNSS_IN_SPACE (2017): technical contribution
RADPARK (2017): technical contribution
REVIVE-A European project (2016): technical contribution
UpSTART (2016): technical contribution.
Coupled-ETC (2012): technical contribution
ULTRAMUMO (2012): technical contribution
SDR Hardware Platform Development (2011): technical contribution.
DEMUMO (2011): technical contribution.
LTE LISTEN MODE (2010): technical contribution
MUMO (2007): technical contribution
ORCID ID: https://orcid.org/0000-0001-6161-6747
project code: FIT-330301-2004-04.