Nikolaos Bartzoudis

Nikolaos Bartzoudis

Head of Department, Senior Researcher

Division: Communication Technologies
Category: Research
Phone: +34 93 645 29 12     Ext: 2136
Fax: +34 93 645 29 01
Email:

Summary

Nikolaos Bartzoudis (Alexandroupoli, Greece 1976) is a Senior Researcher and head of the PHYCOM department at CTTC. Nikolaos obtained his B.Sc. in Electronic Engineering at the Technical Educational Institute of Thessaloniki (Greece, 2000). He then pursued postgraduate studies and received his M.Sc. degree (in Digital Communication Systems) and Ph.D. degree (in dependable embedded systems) from Loughborough University (UK, 2001 and 2006 respectively). Before joining CTTC (January 2008), Nikolaos has worked 2 years as Research Assistant (Loughborough University , UK, 2001-2003) implementing reconfigurable hardware solutions for Active Networks and as a Senior Research Officer (University of Essex , UK, 2005-2008) implementing a flexible low-cost sensor-processing node with built-in self-testing utilities. At CTTC Nikolaos was promoted twice, from Senior Research Engineer to Research Associate (10/2008) and then to Senior Researcher (04/2013). Nikolaos has been/is principal investigator and project manager in 5 funded R&D projects (ReproRun, ITERATE, AEThER, BeMImoMAX, GEDOMIS-ADCOMM). He has also participated in more than 10 other R&D projects funded by public authorities (EC, Spanish government and EPSRC) or the industry. Nikolaos has supervised M.Sc. and Ph.D. students, served as mentor in the Google Summer of Code 2015, gave invited lectures, participated in industrial panels, acted as proposal evaluator and coordinated live demonstrations of prototypes in various events. Nikolaos also possesses hands-on knowledge of the entire technology transfer cycle.

Nikolaos has long experience in real-time baseband prototyping for spectral and energy efficient 4G/5G systems, which encompasses:

- Advanced RTL design techniques using hardware description languages (e.g., VHDL) & schematic-entry SW tools
- HW-SW co-design for FPGA-based SoC devices
- Working with high sample rates and/or under dense FPGA design constraints
- Board-level code integration (firmware), laboratory testing and debugging
- KPI-driven experimental validation
- Examples: multi-carrier (e.g., OFDM, FBMC) and multi-antenna systems, waveform cohabitation, cognitive/reconfigurable radio, hardware-assisted Software Defined Radio

1. Duties as Head of Department

- Define together with the Division Head the scientific and technical objectives of the Department.
- Take all necessary actions to guarantee the Department’s financial sustainability (through competitive funding proposals, industrial offers etc.).
- Manage the effort devoted to R&D projects for Department members.
- Recruit personnel when funds are made available.

2. Duties as technical team leader

- Supervise and coordinate the development and experimental testing of computational intensive DSP algorithms/systems applying high speed digital designs techniques and hardware-software co-design practices.
- Motivate or lead the dissemination of results produced in projects.
- Networking activities leading to national and international collaborations, materialized as publications or demonstrations (e.g., with Intel (Munich), CEA-Leti, Airbus DS (Paris), SMEs and other academic institutions).
- Principal Investigator & project manager in proposals and projects respectively.

3. Other assignments at CTTC

- Member of CTTC’s equality committee (06/2016 – current time).
- Participating in CTTC’s WG on Human Resources Strategy for Researchers (since 10/2018).

4. Grants and awards

- Ph.D. studentship, Loughborough University, Department of Electronic & Electrical Engineering, UK (01/11/03 – 31/07/05).
- M.Sc. grant (as part of a training-course) Essex University, Department of Computing and Electronic Systems, UK (01/10/06 – 31/01/07).
- “Torres Quevedo” grant, Spanish ministry of education and science, National plan of scientific research, technologic development and innovation. Ref: PTQ-08-01-06441.

5. Invited talks & lectures

- “Extending the ns-3 LTE module for SDR: a HW-SW function split paradigm”, 13th EAI International Conference on Cognitive Radio Oriented Wireless Networks (CROWNCOM 2018), – Workshop in “Open radio platforms for 5G research and beyond”, September 18-20, 2018, Ghent, Belgium.
- “Partitioning and distributing communication stack functions of 5G wireless hotspots”, EuCNC 2016, 5G-PPP Workshop on 5G Physical Layer Design and Hardware Aspects Below and Above 6 GHz, Athens, Greece 27 June 2016.
- “To SDR or not to SDR? Hardware accelerators and co-processors for SDR systems“, invited talk, panel session organized by National Instruments, Industry Forum at GLOBECOM 2014, Austin, TX, USA, December 2014.
- “Wideband Digital Predistortion Techniques”, IMS 2014, Tamba, FL, USA, talk given by Professor Pere Gilabert UPC with personal contributions, industry workshop entitled “Recent Advances in Digital Pre-Distortion”.
- “Flexible multicarrier waveforms: implementation issues and baseband processing technologies”, SUPELEC, Rennes, France, May 2014, NEWCOM# Spring School “Flexible Multicarrier Waveforms for Future Communications Wireless Networks “.
- “Prototyping the Physical Layer of Modern Wireless Communication Systems: Development Flows, Challenges and Pitfalls”, CTTC, Castelldefels, Spain, November 2013, NEWCOM# Winter School “Beyond 4G Networks in Cities: From Theory to Experimentation and Back”.
- Lecture on “Advanced digital design techniques using FPGAs”, UNLP, Argentina, August 2011.
- Lecture on “Commercialization roadmap for FPGA IPs”, UNLP, Argentina, August 2011.
- I gave several additional talks at CTTC as part of its established weekly seminar framework.

6. Reviewer

- IEEE Transactions on: Circuits and Systems, Wireless Communications, Vehicular Technology, Computers, Parallel and Distributed Systems, Industrial Electronics, Instrumentation & Measurement
- IEEE Magazines: Communications, Wireless Communications, Vehicular Technology, Micro, Design &Test
- IET: Computers & Digital Techniques
- EURASIP Journal on: Wireless Communications and Networking, Advances in Signal Processing
- Elsevier Journal on: Digital Signal Processing, Physical Communication, Computer Networks

7. Conference TPC member

- BLISS (2008, 2009)
- PIMRC (2009, 2013, 2015, 2016, 2017, 2018)
- EST (2010, 2011, 2012, 2013)
- CICS (2011, 2012)
- EUSIPCO 2011
- ISWCS (2014, 2015, 2016)
- SAM 2014
- SSD 2014
- EW 2014
- URSI 2015
- ICC 2015
- ICT 2019
- CrownCom 2019
- SET CAS 2015
- EUCNC (2016, 2017, 2018, 2019)

8. Scientific & professional memberships

- Senior IEEE member (Member of the IEEE Communication and Signal Processing Societies, Founding member and vocal of the IEEE Sensors Council (Spanish Chapter)).
- Deputy member of the 5G-PPP Technical Board (since 09/2015).
- Member of a CTTC research group recognised by the local Catalan government since 2009.

9. Specific experience with SDR pltaforms

Xilinx ZC706 board combined with the AD-FMCOMMS3 evaluation kit

- AD9361 RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs
- TX band: 47 MHz to 6.0 GHz
- RX band: 70 MHz to 6.0 GHz
- Projects: EMPhAtiC, AEThER, Flex5Gware, ReproRun

USRP N210 connected to a PC/laptop

- WBX RF front-end: 50-2200 MHz
- Rx/Tx: 40 MHz BW
- Application: IEEE 802.11a/g/p GNU Radio Companion
- Project: NEWCOM#

USRP X310 using the Ettus RFNoC framework

- Xilinx Kintex-7 (XC7K410T)
- WBX-120 USRP Daughterboard (50 MHz – 2.2 GHz, 120 MHz BW)
- Project: ReproRun

Xilinx Zynq UltraScale+ MPSoC ZCU102 board combined with the AD-FMCDAQ2 board

- AD9680 dual, 14-bit, 1.0 GSPS, JESD204B ADC
- AD9144 quad, 16-bit, 2.8 GSPS, JESD204B DAC
- Projects: Flex5Gware, ITERATE