ReproRun - Reprogramming FPGA devices at run time using partial reconfiguration in SDR platforms (ReproRun)

Start: 01 September 2018
End: 31 May 2019
Funding: European
Status: Ongoing
Division: Communication Technologies
Department: Physical-layer Implementation of High Performance Communication Systems (PHYCOM)

CTTC participates as a third party in the H2020 ORCA project (subcontracted by Imec), implementing the ReproRun project, which was one of the winner proposals in the 2nd ORCA Open Call for Extensions. The goal of ReproRun is to provide a dynamic partial reconfiguration framework for FPGA devices used in software defined radio (SDR) systems. The working assumption is that the FPGA devices embed a hardwired or soft processing system (PS) which is interconnected with the programmable logic (PL) using a standard embedded bus interface. In this respect, each partial bitstream targeting a reconfigurable region of the PL area comes with firmware and other software functions (for control and programing purposes) running at the PS side. The partial reconfiguration is triggered by a remote host. Then, a controller application at the PS side of the SDR platform (Processor 1) will parse the remote host commands and fetch the partial bitstreams and respective firmware from the remote location using a standard http or ftp connection. In order to apply a run-time partial reconfiguration, ReproRun makes use of all the related building blocks (e.g., the Xilinx partial configuration controller), design guidelines and tools offered by Xilinx, which guarantee a seamless operation of the static part of the PL design. Similarly, ReproRun will guarantee the run-time update of the firmware without interrupting the functionality of other software processes running in the PS (Processor 0), by employing a specialized controller that makes use of an asymmetric multiprocessing framework (and related techniques).

  • IMEC
  • Font, Oriol
  • Harbanau, Pavel